The disclosed embodiments relate to a semiconductor device, and more particularly, to a three-dimensional (3D) semiconductor device including three-dimensionally arranged memory cells.
Along with decreasing sizes of semiconductor devices, the integration of two-dimensional (2D) semiconductor devices (or planar type semiconductor devices), in which a plurality of memory cells are two-dimensionally arranged, is reaching a limit. To overcome such an integration limit, although three-dimensional semiconductor devices (vertical type semiconductor devices), in which memory cells are three-dimensionally arranged, are proposed, more complicated and precise process control is required than in the case of two-dimensional semiconductor devices.